Several basic device architectures exist in the art for constructing image sensor arrays. Two of these are the frame transfer and line-address architectures. These architectures generally have a plurality of CCD elements arranged in rows and columns. For each CCD photosite well, an additional well separated by a barrier needs to be fabricated adjacent to the well for receiving the stored charge. Further, pixel density is decreased by the requirement of channel stops and well barriers. In certain of these devices, drains are formed in the channel stops to prevent blooming, and this occupies further array area.
Another class of imagers is arranged according to the interline transfer architecture. These devices comprise a plurality of photosites that can be either empty CCD wells or photodiodes. The photosites are separated by columns of CCD elements provided for readout of the signal. The necessity for the CCD columns decreases pixel density. Channel stops and barriers are required since CCD elements are used in the structure, and this further decreases pixel density.
Yet another class of devices uses an X-Y architecture, wherein each cell or element is individually addressed in the X and Y direction in order to read it out. Conventional X-Y architectures include charge injection devices (CIDs), MOS transistor devices and, more recently, charge-modulated transistor devices. In the CID device, two gates are formed, one connected to a column line, and another connected to a row line. CID arrays have long readout leads, and therefore, have a large parasitic capacitance. This in turn lowers the dynamic range of the device because of the kTC noise associated with the long, high-capacitance readout lines. Further, since each cell is required to be separately read out, the readout of an entire row of cells takes a considerable time. The high-density television (HDTV) format requires that the addressing and readout of an image sensor array used in connection therewith be done within a standard 53.5-microsecond period. Thus, if there are 1000 elements in a row of a CID array device that is operated in the HDTV format, each element in the row must be addressed and read out in 53.5 nanoseconds. This is very difficult to accomplish because of the RC time constant associated with charging up the readout lines, which in turn limits the size of CID image sensor arrays. Further, the relatively large time necessary to read out the array increases the opportunity for charge to leak from nonaddressed elements to addressed elements, thus causing smear.
MOS transistor arrays have the same problems as CID arrays relative to their long, large-capacitance sense lines. In addition, the charge from each address element is not amplified, but is instead read out directly on these sense lines. Pixel density of these device arrays is reduced by the requirement of forming either one or two transistors at each photosite for addressing purposes.
Recently, a charge modulated device has been proposed by T. Nakamura, K. Matsumoto et al. in their article "A New MOS Phototransistor Operating in a Non-Destructive Readout Mode," Japanese Journal of Applied Physics, Vol. 24, No. 5, pp. L323-325 (May, 1985). This proposed sensor array has the same X-Y architecture as the CID and MOS architectures mentioned above, and thus suffers the same dynamic range and speed problems as the other X-Y addressed architectures.
Variations in the manufacturing of these conventional image sensors produce an undesirable "pattern noise." The pixel density constraints and the architectural schemes conventionally described in connection with these devices do not allow sufficient flexibility for such operations as electronic zooming, panning, and automatic exposure control Given the necessity of small pixel size and relatively fast addressing and readout, the individual addressing of each element in a row having a large enough number of elements for good resolution has not been accomplished by conventional devices within the HDTV horizontal readout period.
Further, recently introduced charge modulated transistor elements modulate an output current, rather than a voltage. The signal current from these elements will vary both as a function of the element's size and its intrinsic threshold voltage. To reduce pattern noise from these two sources, it has been necessary to control element-to-element variations in these parameters to tolerances of one-half percent or better. Such tight control gets progressively more difficult as the pixel size decreases.
A need therefore exists in the industry for an image sensor array in which fabrication variations as to size, doping and threshold voltage among the sensor elements therein can be eliminated as a source of pattern noise. Further, a need in the industry has existed for a transistor image array architecture that will allow electronic zooming, panning and exposure control operations, and will be able to operate in high-density television applications. Finally, a need has arisen in the industry for an image sensor array having good blooming control and no measurable smear.